1. Technical Field
The present invention generally relates to a method of fabricating semiconductor devices. More particularly, the present invention generally relates to a method of forming interconnection lines for semiconductor devices.
A claim of priority is made to Korean Patent Application No. 2004-0009120, filed Feb. 11, 2004, the disclosure of which is hereby incorporated by reference in its entirety.
2. Discussion of the Related Art
Higher integrated semiconductor devices demand reliable interconnection lines. Copper (Cu) is a material used for interconnection lines. Copper has a lower resistivity property compared to aluminum (Al). Therefore, the use of copper tends to suppress the RC delays associated with aluminum interconnection lenses. In addition, copper has a relatively high melting point compared to aluminum, and therefore has good relative resistance to electro-migration and stress-migration.
Conventionally, a dual damascene process is used to form copper interconnection lines. Advantages of the dual damascene process include the formation of multilayered metal interconnection lines and contacts between interconnection lines at the same time with no step height differences due to metal interconnection lines. The dual damascene processes include (1) a first via hole fabrication, and (2) a first trench fabrication. Generally, the first via fabrication is used because the size of a via hole can be maintained even if a double misalignment occurs during fabrication. A conventional dual damascene process is disclosed, for example, in U.S. Pat. No. 4,789,648.
However, a lower conductive region exposed by a via hole may be damaged during an etch process used to form a trench. Therefore, in order to prevent etch damage, a via hole filling material is formed inside the via hole prior to application of the trench forming etch process. A conventional dual damascene process employing such a via filling material is disclosed, for example, in U.S. Pat. No. 6,057,239.
In the dual damascene process using the via filling material, it is preferable to completely remove the via filling material from the via hole, and possibly from an associated insulating layer, after forming the trench. One method of removing the via filling material by a plasma etch process using carbon tetra fluoride (CH4) as an etch gas is disclosed, for example, in U.S. Pat. No. 5,705,430. Generally, the via filling material can be removed by a wet etch process. If the via filling material is not completely removed, a resulting etch residue on the insulating layer may cause a step height difference in a subsequent chemical-mechanical polishing process. Such a step height difference may cause interconnection lines to be formed in a non-uniform manner. Further, etch residue inside the via hole may cause deterioration in the electrical performance characteristics of the interconnection lines.